GCN Insider | Trends and technologies that affect the way government does IT
By now, every IT person should know that when data is at rest, we measure it in bytes. And when it is moving around a network, the custom is to measure the rate in bits. But did you know that as it moves across a motherboard bus, the rate should be specified in transfers, or, at today's rates, gigatransfers?
All this is important to know in reference to the news that the PCI Special Interest Group has released version 2 of the PCI Express specification (PCIe 2.0). The specification doubles the transfer rate of cards on a PCI Express bus to 5 gigatransfers/second, from 2.5GT/s.
A gigatransfer is the amount of data that passes along a bus within a given clock cycle, said Al Yanes, chairman and president of the PCI SIG. Since PCIe 2.0 doubles the clock rate of the PCI controller, the data rate has doubled as well. A PCIe 2.0 card that uses all 16 lanes of its slot can transfer as much as 16GB/s.
Developed by Intel Corp., PCI has long been the standard internal interconnect for communications between the PC systems and their add-on components, such as graphics cards. Introduced a few years ago, PCI Express increased throughput by physically moving data serially across the bus, rather than in parallel. Now, this new version increases the throughput again, while reducing the size needed for PCI slots. It also allows components to cut back on the amount of electricity they receive, should they not need as much to operate. PCIe 2.0 slots can also work with PCIe 1.0 cards.
Yanes notes that it will be about a year before we actually start to see PCIe 2.0 products. In the meantime, the PCI SIG is working on specifications for PCIe cables, which would allow devices to be connected externally through a cable. It is also tackling the problem of standardizing input/output virtualization, the fruits of which should help virtualization software access I/O devices more speedily. It is truly an exciting time for internal PC bus technology.
Joab Jackson is the senior technology editor for Government Computer News.