Chips for the next dimension
The Defense Department is spending millions of dollars to improve the processing performance of integrated circuit chips by stacking them in layers.
'You can only get a certain amount of circuitry in an area of silicon,' said Ken Williams of RTI International in Research Triangle Park, N.C.
Chip developers are shrinking the size of the circuits to get the most out of that space, and the next step in design efficiency is to go up, not out.
'You're building in the third dimension,' said Williams, vice president of RTI's Material and Electronic Technologies Division.
The 3-D interconnect technology is being used in two programs funded by the Defense Advanced Research Projects Agency to improve the performance of infrared sensors and high-speed optical communications. But the technology could result in more powerful chips for all types of computing products, from PDAs and cell phones to desktops and supercomputers.
RTI is planning to host a gathering in October of small chip manufacturers who do not have large R&D budgets, military contractors and government officials.
'We want to bring together the community that could make use of 3-D integration,' Williams said. 'We want to focus on the government's needs.'
RTI acquired the 3-D integration and electronic packaging program when it acquired the research divisions of the former MCNC Research and Development Institute earlier this year.
A number of research facilities are working on similar technologies, and large commercial chip fabricators are believed to be working on it as well, although the companies are keeping quiet about their work, Williams said.
'We think companies like Intel and others are working down that path as a way to keep up the process of Moore's law,' which predicts that processing power will double every 18 to 24 months.
The idea of stacking chips is not new. The challenge is in how the layers are interconnected. Stacking traditional chips to save real estate does not shorten the connections between them, a crucial factor in performance.
The RTI technology drills connections through the silicon from one layer to another, creating massively parallel electrical connections between silicon wafers.
RTI is a subcontractor to Lucent Technologies of Murray Hill, N.J., providing control and drive electronics for array mirrors for optical communications in the Coherent Communications Imaging and Targeting program. DARPA is providing $1.4 million for the second phase of this $13.5 million effort to develop a prototype micro-electromechanical system to correct atmospheric distortion.
Digitally manipulating optical beams with tiny, high-density mirror arrays could enable greater range and higher data rates in ground-to-space communication links. The 3D interconnects let drive electronics be placed directly behind each pixel of the array for high-speed corrections. This could provide multigigabit-per-second uplinks. It also could be used to produce clear, 3-D imaging at distances of more than 1,000 kilometers.
The first layer of a CCIT chip contains the mirror arrays, controlled by MEMS actuators. The second layer contains high-voltage drivers for the actuators and the third layer does processing to correct distortion.
CCIT also could be used for optical weapons targeting systems.Sensitive sensing devices
Layered chips also are being incorporated in DARPA's Vertically Interconnected Sensor Arrays program to produce more efficient and sensitive infrared sensing devices. RTI's share of the program is $1 million. DRS Technologies Inc. of Parsippany, N.J., also is working in the VISA program. As in the CCIT, controls are positioned behind each pixel. The first layer of the chip contains infrared detectors, the second layer is an analog processor and the third is for digital circuits. A fourth layer could be used to process color.
The VISA system could be used in any night vision application.
RTI is producing multilayer chips on a limited basis.
'We're doing some production now for Santa Barbara Infrared Inc., a military contractor' in California, Williams said. RTI would like to set up a pilot production line to produce prototypes for other chip developers. 'We'll teach them how to do it, so they can take the technology back home with them.'
Restricting the functionality of each layer could simplify the production process for multilayer chips.
The current three- or four-layer applications are only the start of layering chips, Williams said. As the technology is perfected, chips with up to 20 or 25 layers could be developed.
In those configurations, dissipating heat generated by the processors could be a problem, Williams said, although 'there are ways to combat that.' Cooling mechanisms could include copper heat sinks penetrating the chips or layers that include coolant. But at four layers, 'that has not been an issue as yet.'