AMD readies new line of energy-efficient server chips
- By Wyatt Kash
- Feb 10, 2010
Advanced Micro Devices is preparing to release two new energy-efficient processor platforms in the first half of this year.
“We’re seeing more interest in performance-per-watt platforms and for highly energy-efficient, cost-optimized platforms,” said Brent Kerby, senior product manager for the AMD Opteron processor.
But AMD also wanted to find a way to build a new series of chips that could evolve, using common design elements that didn’t require new drivers with each new generation.
That’s the idea behind AMD’s new Opteron 6000 and 4000 series processor platforms. The platforms are aimed at what the chip maker is calling a sweet spot between the need for performance and need for maximum energy efficiency.
The new designs will replace AMD’s three-tiered processor product line for servers. The platforms will be compatible with AMD’s forthcoming Bulldozer Core architecture and are designed to provide greater cross-generational consistency and commonality, Kerby said.
The first of the two platforms — the 6000 series, code-named Maranello — is designed for maximum scalability and threading capability in large-scale virtualization installations that typically run, for instance, multiuser database applications. But it also will work well for large, dense deployments in which power concerns are important, such as Web and cloud computing installations.
The 6000 series platform will provide the foundation for eight- and 12-core AMD Opteron 6100 series x86 processors, code-named Magny-Cours, which are due for release in the first quarter of 2010. The 45-nanometer chips come with four memory channels for greater processing efficiency and are designed to support Enterprise Class two-way and four-way servers that use the G34 socket infrastructure. The design means the processor can fit in two-socket or four-socket installations. “So you no longer need to buy a four-socket processor” in instances where a more economical two-socket processor would do the job, Kerby said.
A more advanced, 32-nanometer chip with 12 and 16 cores, code-named Interlagos, is expected to be introduced in 2011.
The other platform, known as the 4000 series, is designed to operate at optimal energy efficiency, targeting large IT infrastructure deployments for which power and cooling cost efficiency are primary concerns. AMD will release two versions of the platform: A low-power version, called San Marino, and an ultra-low power version, called the Adelaide.
Both versions will use AMD’s new line of 45-nanometer, four- and six-core 4100 series processors, code-named Lisbon, scheduled for release in the second quarter of 2010. A 32-nanometer, six- and eight-core processor, code-named Valencia, is slated to be launched in 2011, Kerby said.
The 4100 series processors are expected to be the first to operate at less than 6 watts per core, down from 10 watts per core in the current generation of chips, Kerby said. That’s substantially less than the typical 89 watts consumed by single-core processors AMD offered as recently as 2003, he said.
Kerby declined to discuss AMD’s pricing plans for the new chips. But the new performance gains and lowered energy costs are expected to please information technology managers and facilities managers who are keeping an eye on utility costs.
"Overall I believe AMD's roadmap is a smart one for the company as well as good for the consumer," observed Daniel P. Harrington, a research analyst at IDC specializing in enterprise servers.
"The 4000 and 6000 lines were designed specifically with customer application in mind, from those looking for performance or high density, to those looking for extreme power efficiency," he said.
"At 12 cores, the Magny-Cours platform represents an significant jump in core-count to the market. The exponential jump in core counts year to year is expected to cause somewhat of a disruption in the server market as users begin to look at these solutions as a value proposition as opposed to the legacy thinking of x86 as a commodity," he said.
"What will be interesting to see is how these products are priced compared to their other processor lines," Harrington said. "My belief is that it will be priced at a premium ... as to not cannibalize their lower core (products). At both 2P (processor) and 4P configurations, users are expected to enjoy a significant performance boost, especially those running highly parallel applications," Harrington said.
Wyatt Kash served as chief editor of GCN (October 2004 to August 2010) and also of Defense Systems (January 2009 to August 2010). He currently serves as Content Director and Editor at Large of 1105 Media.