Internet on a chip: MIT team aims for massively multicore processors

Researchers at the Massachusetts Institute of Technology are developing methods for multiple processors on a microchip to share data, working in a manner similar to the Internet.

If it is successful, multi-processor chips will be able to operate more efficiently and effectively, allowing engineers to greatly increase the number of processors per chip.

Current chip designs could have six to eight processors, or cores, communicating with each other via a bus. The only problem with this design is that only one pair of cores can communicate at a time, which is a major hurdle for future computing designs, which call for scaling up chips to have hundreds or thousands of cores.

Related stories:

Single-atom transistor: The future of computing?

IBM's experimental chip 'thinks' like a human brain

An MIT team, led by associate professor of electrical engineering and computer science Li-Shiuan Peh, is working on ways to make cores share information by bundling them into packets. Each core would have a router and would send packets by any of several paths, depending on network conditions, MIT News reports.

In a paper to be presented at the Design Automation Conference in June, Peh and her colleagues will discuss the theoretical limits of the efficiency of packet-switched on-chip communication networks based on measurements they conducted on a test chip operating close to those limits.

Multicore chips run faster than single processor chips by dividing computing jobs among several cores simultaneously. These teamed cores sometimes need to share data, but the core count on existing chips has been low enough that only a single bus was needed to handle the load.

However, this bus design has reached its limit, Peh said in a statement.

Buses require a lot of power to push data along the wires linking eight to 10 cores, Peh said. Her proposed design has cores communicating with only the four adjacent cores, which allows for shorter wires and lower voltage needs.

Another challenge facing on-chip networks is that inter-core data packets have to stop at every router on the chip. If two packets simultaneously arrive at the same router, one must be stored in memory while the other is processed, Peh said, adding that many industry engineers fear that any advantages offered by packet switching will be offset by the added complexity of the system.

To address these concerns, Peh and her team have developed two techniques: virtual bypassing and low-swing signaling.

In traditional Internet packet routing, routers inspect each arriving packet’s addressing information before determining which path to send it on. In virtual bypassing, routers send an advance signal to the next router on the path, presetting it and allowing the packet to speed along without any added processing. In the test chip Peh's team developed, she said, virtual bypassing allowed it to run at speeds very close to the maximum predicted rates.

For low-swing signaling, the team developed a circuit that reduced the shift between high and low voltages from one volt to 300 millivolts. When data is transmitted over a network, it moves as high and low voltages. By using virtual bypassing and low-swing signaling, the MIT test chip used 38 percent less energy than other packet-switched test chips.

More work is need before the test chip’s power use gets as close to the theoretical limit as its data rate does, but Peh said it still is “orders of magnitude” more efficient than a bus in power consumption.



  • 2020 Government Innovation Awards
    Government Innovation Awards -

    21 Public Sector Innovation award winners

    These projects at the federal, state and local levels show just how transformative government IT can be.

  • Federal 100 Awards
    cheering federal workers

    Nominations for the 2021 Fed 100 are now being accepted

    The deadline for submissions is Dec. 31.

Stay Connected