brain in a circuit board (Sergey Tarasov/Shutterstock.com)

Machine learning on the fly

When the Defense Advanced Research Projects Agency announced its first Grand Challenge in 2002, the idea of driverless cars racing 150 miles across the Mojave Desert seemed impossible. With its latest Grand Challenge, DARPA hopes make real-time machine learning as unremarkable as autonomous vehicles are today. 

Partnering with the National Science Foundation, DARPA's Real-Time Machine Learning (RTML) program  is offering $10 million in funding for "the creation of a processor that can proactively interpret and learn from data in real-time, solve unfamiliar problems using what it has learned, and operate with the energy efficiency of the human brain."

While real-time machine learning is available for applications like computer vision and speech recognition, the next generation of autonomous vehicles, military applications, health care informatics and business analytics depends on real-time learning, prediction and automated decision-making.

DARPA aims to develop small, lightweight, low-power systems that use artificial intelligence to rapidly learn and adapt to new circumstances in real time.  Such an accomplishment calls for "ground-up" development of new chips, architectures and algorithms specifically designed for machine learning, it said in a March 15 broad agency announcement.

The plan is for NSF to manage "path finding research," while DARPA deals with the tools and circuit development that can address all stages of training and can be performed in real time from a continuous stream of new data. The ML approaches are being developed in a distributed setting so that they can closely approximate a centralized cloud-based environment. 

The DARPA program is split into two, 18-month research phases. The first will create "no human in the loop" tools (hardware compilers) that will, in turn, enable fully automated generation of ML-specific chips directly from high level source code, thereby eliminating the high cost of application specific integrated circuits. The second phase builds on the compiler infrastructure developed in Phase 1 and calls for support for hardware optimization for two real-time machine learning demo applications -- future high-bandwidth wireless communication systems and high bandwidth image processing in systems with size, weight and power constraints.

Independent of DARPA, NSF will independently select projects for 36-month awards. When DARPA's  Phase 1 hardware compiler becomes available, awardees will have the option to evaluate those proposed new RTML approaches. Meanwhile, techniques and results produced by NSF awardees during the first 18 months will be made available to DARPA project teams for their Phase 2 efforts exploring architectures and circuits that will enable RTML.

About the Author

Susan Miller is executive editor at GCN.

Over a career spent in tech media, Miller has worked in editorial, print production and online, starting on the copy desk at IDG’s ComputerWorld, moving to print production for Federal Computer Week and later helping launch websites and email newsletter delivery for FCW. After a turn at Virginia’s Center for Innovative Technology, where she worked to promote technology-based economic development, she rejoined what was to become 1105 Media in 2004, eventually managing content and production for all the company's government-focused websites. Miller shifted back to editorial in 2012, when she began working with GCN.

Miller has a BA and MA from West Chester University and did Ph.D. work in English at the University of Delaware.

Connect with Susan at smiller@gcn.com or @sjaymiller.

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