AMD formally launched its sixth-generation EPYC server processor, codenamed Venice, at the company’s Advancing AI 2026 conference held at Moscone West in San Francisco on July 22 and 23, marking the commercial debut of its 6th Gen EPYC processors, the first chips to ship with the Zen 6 architecture and the first high-performance server CPUs built on TSMC’s 2nm process.
A generational leap in core count and bandwidth
The flagship Venice configuration scales to 256 cores, a 33% jump over the current 192-core EPYC Turin lineup. AMD claims more than a 70% improvement in overall performance and efficiency versus the current EPYC Turin chips, along with more than a 30% increase in thread density.
Those figures represent one of the largest single-generation gains the company has posted since Zen first upended the server market in 2017.
Venice is built on TSMC’s 2nm process, making it the first high-performance computing processor to reach production on that node. Manufacturing is currently ramping in Taiwan, with future production planned at TSMC’s Arizona facility.
Venice introduces a new SP7 socket, and is the first AMD EPYC chip with PCIe Gen 6. Top Venice configurations support 16-channel memory delivering up to 1.6 TB/s of bandwidth.
Helios: a rack-scale AI platform built around Venice
The launch begins with 6th Gen EPYC processors, codenamed Venice, rather than consumer Ryzen CPUs. EPYC Venice anchors AMD’s Helios rack-scale AI platform, where the processors operate alongside AMD Instinct MI455X accelerators and AMD Pensando networking hardware.
Advancing AI 2026, AMD’s annual gathering for the global AI community, took place July 22, 23 in San Francisco, bringing developers, customers, and channel partners together. The event was built around a keynote, expo, and more than 100 sessions including breakouts, tech talks, and workshops.
AMD has confirmed that its new EPYC CPUs deliver more than a 30% increase in thread density and over 70% improvement in performance and efficiency. The processors also include more AI pipelines and support for new AI data types.
That combination is designed to let a single Venice-based server handle both traditional enterprise x86 workloads and the dense matrix math that powers large-scale AI inference, without requiring separate accelerator nodes for each task.
Why enterprise buyers are watching the x86 argument closely
AMD CTO Mark Papermaster described the upcoming CPUs as optimized for traditional x86 enterprise workloads, noting that enterprise customers are not moving away from x86.
Rather than replacing conventional computing models, the Zen 6 architecture has been designed to further optimize standalone x86 workloads while complementing AMD’s expanding portfolio of AI-focused hardware.
The timing is pointed. NVIDIA’s Blackwell platform has drawn enormous capital commitments for pure AI compute, a dynamic already reshaping how chipmakers pitch their roadmaps, as seen in the throughput gains Blackwell demonstrated in real-time AI workloads.
AMD’s counter-argument with Venice is that the data center does not have to choose: a single 2nm socket can run the database, the inference layer, and the HPC job in the same rack.
At the RAISE Summit in Paris in early July, Papermaster confirmed that the sixth generation of Zen architecture would be officially unveiled on July 22 and 23, 2026 at the Advancing AI event at the Moscone Center in San Francisco. AMD has now reached its sixth generation since the original Zen processors launched in 2017, a cadence that has taken the company to a record 46.2% of x86 server CPU revenue in the first quarter of 2026, according to Mercury Research.
Consumer Zen 6 still on the horizon
Consumer desktop CPUs based on the Zen 6 architecture are expected to debut later, with industry forecasts pointing to late 2026 or possibly an official unveiling during CES 2027. This staggered rollout follows AMD’s familiar product strategy: enterprise processors typically introduce new architectures and manufacturing nodes before those innovations filter into Ryzen desktop processors.
The enterprise focus also explains the surge in enterprise AI inference demand that has driven chipmakers to prioritize data-center silicon.
AMD framed its Advancing AI announcements against a total high-performance and adaptive computing opportunity approaching $2 trillion by 2030 , and Venice lands squarely in the middle of that spending wave. AMD will be counting on Venice to capture a larger slice of it before rival server platforms close the core-count gap.
