Every smartphone, laptop and AI server on the planet runs on a chip. Most Americans have heard chips are getting smaller. Almost nobody knows what happens when they literally cannot get any smaller the old way.
That wall has a name in physics. It is roughly one nanometer, about the width of ten hydrogen atoms lined up side by side.
Engineers have been creeping toward it for decades. This summer, one lab said it crossed it. And the way they did it changes everything about how a transistor is actually built.
The number on the box has been shrinking for 60 years, and here is what that really means
When a chip company says “2nm” or “3nm,” they are describing the size of the tiny switches, called transistors, crammed onto a slice of silicon.
More transistors means more computing power and less electricity consumed. Gordon Moore observed in 1965 that transistor counts doubled roughly every two years, a rhythm that held so reliably it became known as Moore’s Law.
The problem is geometry. Flat transistors are running out of room on a 2D surface, and quantum physics starts causing leakage errors once features shrink below a certain point.
What a transistor actually looks like, and why making it flat is no longer enough
Previous leading-edge chips use “nanosheet” transistors, a gate-all-around design developed by IBM and introduced in 2017, which now underpins the industry’s 3nm and 2nm chips.
A nanosheet transistor is essentially a thin ribbon of silicon lying on its side, with electrical contacts wrapping around it. It is an elegant solution. It is also, physically, almost as thin as it can go.
The industry has known for years that the z-axis, height, depth, the third dimension, was the only room left to grow into.
The race to the angstrom era has a frontier that only a handful of labs have ever touched
Intel and TSMC are currently racing toward 1.4nm chips, with volume production targeted for later this decade.
That race has attracted enormous investment. Intel is ramping capacity at Fab 52 in Chandler, Arizona, making chips on its 18A node, meant to rival TSMC’s 2nm. You can read more about that competition in our coverage of AMD’s EPYC Venice on TSMC 2nm.
But even those cutting-edge nodes are still essentially flat designs. The transistors sit in a plane. They do not stack.
IBM’s nanostack architecture is the hidden 3D mechanism that just broke the 1nm floor
On June 25, 2026, IBM unveiled the world’s first sub-1 nanometer chip technology, at the 0.7nm node, built with a “nanostack” 3D architecture.
Nanostack extends the prior nanosheet design by stacking and staggering transistors vertically, exploring the z-axis for density gains beyond what 2D scaling can offer. Each stacked layer can use a different semiconductor channel material, letting the NFET and PFET channels be optimized independently.
A key enabler was a new ultra-thin dielectric wafer bonding technique. The method bonds two wafers into a multilayered structure with very few defects, producing a true 3D transistor that testing has shown to be scalable.
The result: nearly 100 billion transistors on a chip the size of a fingernail, roughly twice the density of IBM’s 2nm chip from 2021. Transistor features are smaller than the width of a DNA strand, which measures about 2.5 nanometers according to the National Nanotechnology Initiative.
The chip is projected to deliver up to 50% more performance or 70% greater energy efficiency than IBM’s 2nm node.
When a lab demo reaches a factory floor, the chips in your pocket and your AI bill will both feel it
IBM does not manufacture commercial logic chips at volume itself. It pioneers architectures and transfers know-how to partners; Samsung and TSMC are among the manufacturers that have adopted IBM’s nanosheet technology, and the company is also working with Japan’s Rapidus on 2nm production.
IBM is not yet disclosing how it will commercialize nanostack, and its near-term focus remains helping partners scale today’s 2nm technology. IBM’s 2nm chip, unveiled in 2021, is only now approaching volume production five years later.
The AI workload angle is measurable. At VLSI 2026, IBM demonstrated 40% SRAM scaling with the nanostack architecture, and denser on-chip memory directly reduces the memory-bandwidth bottlenecks that slow large AI models.
That matters for the AI factory buildout now consuming billions in capital. Our earlier look at NVIDIA’s Vera Rubin chips shows just how hungry next-generation AI accelerators are for every performance gain a new node can deliver.
IBM estimates an AI accelerator built on 7 angstrom technology could deliver roughly 7,000 TOPS, compared to about 1,500 TOPS for today’s accelerators, and training runs that now take three months could shrink to roughly two weeks.
The transistor has been flat for most of computing history. Nanostack points up, and that single direction change may keep the industry’s performance curve climbing for another decade.
